1. Technical Field
The invention relates generally to data processing systems (Class 364), and more particularly relates to performing floating point computations on exponents (Subclasses 748 and 753).
In even greater particularity, the invention relates to the conversion of biased exponents from single/double precision to extended precision. In an exemplary embodiment, the conversion technique is implemented in the FPU of a 486- class microprocessor where the FPU performs floating point computation compatible with the IEEE 754 standard.
2. Related Art
The IEEE 754 Standard For Binary Floating Point Arithmetic defines four basic formats: Single, Single Extended, Double, and Double Extended. These formats are defined by a format width (total number of bits), an exponent width (bits of exponent), and an exponent bias--each format includes a leading sign bit.
______________________________________ Format Exp Width Width Bias ______________________________________ Single 32 8 +127 Single .gtoreq.43 .gtoreq.11 Unspecified Extended Double 64 11 +1023 Double .gtoreq.79 .gtoreq.15 Unspecified Extended ______________________________________
Microprocessors commonly include a separate floating point unit (FPU) to perform floating point computations using floating point formatted data--the microprocessor core routes all floating point instructions to the FPU for execution. Internal to the FPU, computations are typically performed using the extended format to allow for greater accuracy in computation (i.e., reducing accumulated rounding error).
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: high performance conversion of single and double precision formatted biased exponents to corresponding extended biased exponents.
In executing a floating point instruction, the microprocessor core supplies the FPU with instruction opcode and operand data. Operand data is supplied in the data format used by the microprocessor--current 32-bit x86 microprocessors (386, 486, 586), can supply floating point operands in single precision (32 bit), double precision (64 bit), or extended (80 bit) formats.
In the FPU, SP (single precision) and DP (double precision) floating point operands are converted to the extended (80 bit) format for internal use in performing floating point computations. After the floating point computation is complete, the floating point result can then be converted from extended to corresponding SP or DP format in a final rounding operation.
Note that the IEEE Standard specifies the exponent formats for single and double precision (8 and 11 its respectively), but only specifies a minimum exponent range for extended formats (.gtoreq.11 and 15 bits respectively). For the x86 architecture, the exponent range for the extended format used for both SP and DP is 15 bits.
Converting SP and DP format operands to the corresponding internal extended format involves converting both the exponent and the fraction portions.
Exponents are biased to allow magnitude comparisons to be performed using integer comparators (in addition, zero is represented as a number of all zeros). While the IEEE Standard does not specify the bias factor to be used with the extended format, the common approach is to use a bias of +16383.
Current FPU implementations of biased exponent conversion hardware use an adder--the adder accomplishes the conversion by subtracting an exponent bias for SP/DP, and adding the bias for extended--to convert SP to extended the bias is +3F80(hex), and to convert DP to extended the bias is +3C00(hex). See, for example, U.S. Pat. No. 4,949,291 entitled "Apparatus and Method for Converting Floating Point Data Formats In A Microprocessor" which describes a conventional approach to exponent conversion using an adder to add a conversion constant obtained from a constant ROM. This addition/conversion operation requires propagation through the adder.
Reducing the delay associated with the addition operation in converting to/form biased extended exponent formats would increase FPU performance.